1. Field of the Invention
The present invention relates to a semiconductor device fabrication method and its fabrication apparatus.
2. Description of the Related Art
A recent semiconductor integrated circuit device is extremely miniaturized and smoothness of the surface of a Si substrate does not catch up with miniaturization of a gate length. Therefore, it is considered that the unevenness of the surface of the Si substrate is a cause of gate withstands voltage trouble, current leak trouble, and refresh trouble of a random access memory.
The following are conventionally generally performed to flatten the surface of a Si substrate.    (1) The surface of the Si substrate is plane-polished to remove a surface flaw or unevenness which is produced when the Si substrate is sliced from ingot.    (2) The Si substrate is immersed in acid or alkali to remove a working strain layer on the surface of the wafer flattened to a certain extent through the above surface polishing and etched.    (3) The Si substrate is roughly polished to remove roughness or uneven thickness in both sides of the surface and back of the Si substrate.    (4) The Si substrate is finish-polished to flatten the small unevenness of the surface of the substrate.
Japanese Patent Laid-Open No. 11-135464 discloses a method using spin etching using mixed acid (hydrofluoric acid, nitric acid, sulfuric acid, and phosphoric acid) having a high etching rate and a uniform etching characteristic in order to efficiently remove a working strain layer produced through flattening such as plane polishing without damaging the flatness of the surface of a wafer.
However, a conventional the Si-substrate surface-flattening method cannot sufficiently flatten the surface of a substrate. Therefore, it is difficult to reduce gate withstand voltage troubles, current leak troubles, and refresh troubles of a random access memory, which may be due to the unevenness of the substrate surface.
In the case of a present semiconductor device having a gate length of 200 nm or less, reduction of the thickness of a transistor gate oxide film is rapidly progressed and the film thickness of the device is smaller than 4 nm. When the means square roughness of the surface of a Si substrate is 0.2 nm, it is estimated that the maximum unevenness is approx. 2 nm and this occupies 50% of a gate oxide film thickness becomes a level which cannot be ignored for the semiconductor device any longer.
However, the flatness according to the above method ranges between 0.2 and 0.3 nm in terms of the mean square roughness and the present semiconductor device of 200 nm or less is not always sufficiently flattened.
However, the present inventor et al. study the unevenness control (Non-patent Document: “Hydrogen termination structure of heat-NH4F-treated Si (100) surface “written by Yutaka Taniguchi, Yosuke Okamura, Hiroyuki Sakaue, Shouzou Shingobara, and Takayuki Takahagi in preliminary report collection of 49th Japan Society of Applied Physics in Spring, 2002) of Si substrate surface in accordance with the immersion-type wet method using the fluoride ammonium and find that it is possible to reduce the mean square roughness to 0.1 nm. However, as a result of applying the unevenness control to a Si substrate having a diameter of 20 cm, the mean square roughness becomes 0.15 nm. Therefore, when applying the unevenness control to a Si substrate having a diameter of 30 cm which is the main stream of present random access memories, the mean square roughness may be further impaired. Moreover, when the mean square roughness is 0.15 nm, it is insufficient for future reduction of a gate length.
Furthermore, the content of the Non-patent Document can be applied to the surface of a Si substrate according to the prior art. In the case of fabrication of a semiconductor integrated circuit device, however, the roughness of a substrate just before forming a gate oxide film becomes a problem. Before forming a gate oxide film, polycrystalline silicon is formed on the back of a regular semiconductor integrated device for gettering and moreover, a groove is formed on the surface of the device for element isolation and then, an oxide film is embedded in the groove.
The polycrystalline silicon on the back is etched through the fluoride ammonium treatment and unevenness occurs and influences the flatness of a surface tail in the back end step.